Title :
Technology Elements and Chip Design for Low Power Applications
Author :
Hook, Terence B.
Author_Institution :
IBM Microelectron., Essex Junction, VT
Abstract :
We present transistor and technology design considerations specific to low power applications from 90nm to 45nm and beyond. We discuss static power and low standby power (LSTP) transistors, and also touch on dynamic power dissipation and low operating power (LOP) transistors. As semiconductor transistor technology is encountering several intransigent limits (voltage scaling and overdrive, and gate leakage in particular), cost-effective means of producing superior chips are enhanced by chip design techniques as much or more than by silicon technology elements
Keywords :
low-power electronics; power transistors; silicon; 45 to 90 nm; Si; chip design techniques; dynamic power dissipation; gate leakage; low operating power transistors; low standby power transistors; semiconductor transistor technology; silicon technology elements; static power transistors; voltage scaling; Batteries; Chip scale packaging; Gate leakage; Integrated circuit technology; Leakage current; Power dissipation; Silicon; Subthreshold current; Temperature; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0439-8
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346882
