Title :
New encoding scheme for high-speed flash ADC´s
Author :
Kaess, F. ; Kanan, R. ; Hochet, B. ; Declercq, M.
Author_Institution :
Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Abstract :
A new encoding scheme for high-speed flash analog to digital converters using a Wallace tree is described. It provides a global error filtering and its regular topology optimises the signal propagation. Its application to a 5-bit 1.4-GHz Gallium Arsenide analog-to-digital converter is described
Keywords :
III-V semiconductors; analogue-digital conversion; comparators (circuits); gallium arsenide; 1.4 GHz; 5 bit; III-V semiconductors; Wallace tree; encoding scheme; global error filtering; high-speed flash ADC; regular topology; signal propagation; Analog-digital conversion; Computer architecture; Encoding; Error correction; Filtering; Gallium arsenide; Latches; Metastasis; Read only memory; Topology;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.608492
