• DocumentCode
    2388690
  • Title

    SPE2/spl sim/Novel 700/spl deg/C selective epitaxial growth technology for elevated source/drain

  • Author

    Miyano, Kenjiro ; Mizushima, Ichiro ; Hokazono, Akira ; Ohuchi, Kazuya ; Tsunashima, Yoshitaka

  • Author_Institution
    Process & Manuf. Eng. Center, Toshiba Corp., Kanagawa, Japan
  • fYear
    2001
  • fDate
    29-30 Nov. 2001
  • Firstpage
    83
  • Lastpage
    86
  • Abstract
    A novel low thermal-budget process for elevated source/ drain (S/D) was developed utilizing solid phase epitaxy (SPE) followed by vapor phase selective etching. The high temperature H/sub 2/ pre-clean was omitted by the use of oxide mediated SPE (OMSPE). The maximum temperature through the process was only 700/spl deg/C. The vapor phase selective etching could also be performed at 700/spl deg/C. The polycrystalline-Si (poly-Si) gate was protected with SiN barrier so as not to be etched during the selective etching. This process is a potential solution for the elevated S/D structure for 0.1 /spl mu/m devices and beyond.
  • Keywords
    solid phase epitaxial growth; sputter etching; 0.1 micron; 700 C; SPE/sup 2/ process; Si-SiN; SiN barrier; elevated source/drain structure; oxide mediated SPE; polycrystalline Si gate; selective epitaxial growth; solid phase epitaxy; thermal budget; vapor phase selective etching; Amorphous materials; Cleaning; Crystallization; Electrodes; Epitaxial growth; Hafnium; MONOS devices; Oxygen; Temperature; Wet etching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Junction Technology, 2001. IWJT. Extended Abstracts of the Second International Workshop on
  • Conference_Location
    Tokyo, Japan
  • Print_ISBN
    4-89114-019-4
  • Type

    conf

  • DOI
    10.1109/IWJT.2001.993833
  • Filename
    993833