Cost-efficient built-in repair analysis for embedded memories with on-chip ECC

This paper concerns low-cost implementation of built-in repair analysis (BIRA) for embedded memories. As embedded memories become more and more dominant in system-on-chip (SoC) design, it is very crucial to achieve sufficiently high embedded memory yield. Due to the increasing number of diversified embedded memories on chip, external memory testing and redundancy repair analysis become inadequate and the use of BIRA becomes more attractive and even indispensable. The essential challenge of BIRA design is to how to minimize its unnegligible implementation cost without sacrificing the achievable repair rate. The key feature that distinguishes this work from prior work is that, motivated by the fact that almost all the embedded memories use error correction code (ECC) for soft error tolerance, we propose to appropriately leverage such existing built-in error correction capability to enable very low-cost BIRA implementations while maintaining the same and even higher defect repair rate and the same soft error tolerance. With this underlying theme, this paper presents a specific design solution, and its effectiveness and advantages over existing solutions has been successfully demonstrated using computer simulations.