Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain (S/D), named partially-insulated- FinFETs (PI-FinFETs), to control subchannel on the bottom part of the gate in bulk FinFETs and suppress punchthrough and junction leakage currents. We observed that the junction leakage is improved about 50%, drain-induced barrier lowering (DIBL) about 25%, and lifetime of hot carrier effect (HCE) about 1 order in comparison with normal bulk FinFETs. Furthermore, we propose a novel PI-FinFET structure with pad-polysilicon side contact (PSC) in bulk-Si to reduce gate induced drain leakage (GIDL) and increase I_on with improved SCE immunity. The simulation of novel structure shows that I_on, DIBL and GIDL is improved dramatically with the same login comparison with bulk FinFETs. This advanced structure is suitable for the miniaturization of GIDL of bulk FinFETs with improved I_on, I_off and DIBL characteristics