Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits

Author

Liang, Dong-Shong ; Gan, Kwang-Jow ; Su, Long-Xian ; Chen, Chi-Pin ; Hsiao, Chung-Chih ; Tsai, Cher Shiung ; Chen, Yaw-Hwang ; Wang, Shih-Yu ; Kuo, Shun-Huo ; Chiang, Feng-Chang

Author_Institution

Dept. of Electron. Eng., Kun Shan Univ. of Technol., Taiwan

fYear

2005

fDate

20-24 July 2005

Firstpage

78

Lastpage

81

Abstract

This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple-peak NDR device is a very promising device for multiple-valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.

Keywords

CMOS integrated circuits; integrated memory circuits; logic design; multivalued logic; four-valued memory cell; four-valued memory circuit; multiple valued logic; multiple-peak MOS-NDR circuits; multiple-peak MOS-NDR devices; negative differential resistance devices; three-peak MOS-NDR circuit; CMOS process; Circuit simulation; Complexity theory; Design engineering; Gallium nitride; Logic devices; MOSFETs; Resistors; System-on-a-chip; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.66

Filename

1530919