Stress-induced MOSFET mismatch for analog circuits

This paper discusses the stress-induced mismatch for MOS transistors for analog circuits. Hot carrier aging and NBTI stress have been performed on nmos and pmos transistor pairs respectively to study transistor´s matching properties. While there is no evident increase of drain current mismatch for transistor pairs under the exactly same stress conditions, a slight difference in gate or drain voltage or in stress time will aggravate saturation current mismatch which is very critical to the analog circuits. The stress-induced transistor mismatch may be the limiting factor for the mismatch and therefore for the reliability of the analog circuits