Hot-carrier reliability and design of N-LDMOS transistor arrays

The increase in handheld and portable appliances operating in the 20-30 V range have driven the need for IC power management control devices. These circuits combine high performance CMOS and bipolar transistors with a power MOS driver. The n-channel lateral DMOS (N-LDMOS) is a common choice for the driver transistor. Because of high drain voltages used by LDMOS devices hot-carrier degradation is an important reliability concern. This paper focuses on the N-LDMOS hot-carrier test methodology, degradation mechanism and effect of device layout on N-LDMOS hot-carrier performance. This paper differs from previous work in that it describes an N-LDMOS hot-carrier failure mode not yet addressed in the literature and for the first time describes the hot-carrier performance of transistor arrays rather than discrete devices