Title :
Contribution of gate induced drain leakage to overall leakage and yield loss in digital submicron VLSI circuits
Author :
Semenov, Oleg ; Pradzynski, Andrzej ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35 μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield
Keywords :
CMOS digital integrated circuits; VLSI; cellular arrays; integrated circuit yield; leakage currents; 0.35 micron; CMOS digital submicron VLSI circuit; gate induced drain leakage; leakage current; off-state current; standard cell; yield; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; EPROM; Leakage current; Logic testing; MOSFETs; Random access memory; Tunneling; Very large scale integration;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2001. 2001 IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-7167-4
DOI :
10.1109/.2001.993916
