Title :
Wafer level testing of inter-line reliability in copper/low-k structures
Author :
Alers, G.B. ; Harm, G. ; de Felipe, T.Suwwan
Author_Institution :
Novellus Syst., San Jose, CA, USA
Abstract :
In this paper, techniques to measure reliability of inter-line dielectrics (both SiO2 and SiOC) in copper dual damascene structures are described. The failure times for tests of single damascene structures were found to vary by many orders of magnitude depending on the process. A voltage ramp test for inter-line reliability is proposed that is better able to capture the wide range in reliability that can results from process variations in a dual damascene process flow
Keywords :
copper; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; Cu-SiO2; Cu-SiOC; copper dual damascene interconnect; failure time; inter-line reliability; low-k dielectric; voltage ramp testing; wafer-level testing; Aluminum; Compressive stress; Copper; Degradation; Dielectric breakdown; Dielectric measurements; MOS capacitors; Temperature; Testing; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2001. 2001 IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-7167-4
DOI :
10.1109/.2001.993923
