Fabrication of 3D packaging TSV using DRIE

3D stacking of die with TSV (through Silicon Via) connection as well as wafer level packaging of CMOS image sensors (CIS) are becoming very hot topics. While TSV of CIS is definitively a back-end technique, 3D stacking of die through TSV can be done with different strategies: from the via first approach, a front-end process, to the via last approach, a back-end process. Each of these different ways of elaborating the vias has its advantages and drawbacks in terms of electrical performances, refilling materials and cost. They have in common the need to etch the vias. In this paper, we will review the DRIE performances for the definition of the different via shapes, depths, and sizes. A very low temperature (< 150 degC) PECVD process has also been characterized and will be presented for the high demanding packaging of CIS.