Author :
Ernst, T. ; Dupré, C. ; Isheden, C. ; Bernard, E. ; Ritzenthaler, R. ; Maffini-Alvaro, V. ; Barbé, J.C. ; De Crecy, F. ; Toffoli, A. ; Vizioz, C. ; Borel, S. ; Andrieu, F. ; Delaye, V. ; Lafond, D. ; Rabillé, G. ; Hartmann, J.M. ; Rivoire, M. ; Guillaumot
Abstract :
Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed
Keywords :
CMOS integrated circuits; hafnium compounds; titanium compounds; 3D integration process; 80 nm; CMOS; FinFET; GAA; HfO2-TiN; current density; gate all around process; gate stack; nanobeam stacked channels; planar transistors; CMOS process; Charge carrier processes; Current density; Electron beams; Electron mobility; FinFETs; Hafnium oxide; Time measurement; Tin; Transmission line matrix methods;
