A 28 mW, 1.5 V GPS receiver in 0.25 μm silicon-on-sapphire CMOS process

Author

Adamski, J. ; Losser, D. ; Dan, Nemes ; Kuramochi, T. ; Fujita, Kinya ; Pucci, G.

Author_Institution

Peregrine Semicond. Corp., San Diego

fYear

2007

fDate

8-10 Oct. 2007

Firstpage

351

Lastpage

354

Abstract

This paper describes a 28 mW, 1.5 V Global Positioning System (GPS) radio receiver chip implemented in a 0.25 μm silicon-on-sapphire CMOS process. The receiver uses a low IF architecture and achieves a cascaded noise figure of 3.5 dB including the RF SAW filter. The design takes advantage of the matching network integration capabilities and superb isolation properties of Peregrine´s UltraCMOStrade silicon-on-sapphire process technology.

Keywords

CMOS integrated circuits; Global Positioning System; radio receivers; radiofrequency integrated circuits; sapphire; silicon; system-on-chip; GPS radio receiver chip; Global Positioning System; IF architecture; Peregrine UltraCMOS silicon-on-sapphire process technology; RF SAW filter; cascaded noise; isolation properties; matching network integration capabilities; power 28 mW; silicon-on-sapphire CMOS process; size 0.25 μm; voltage 1.5 V; CMOS process; CMOS technology; Global Positioning System; Impedance matching; Matched filters; Noise figure; Noise measurement; Radio frequency; Receivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Technologies, 2007 European Conference on

Conference_Location

Munich

Print_ISBN

978-2-87487-003-3

Type

conf

DOI

10.1109/ECWT.2007.4404019

Filename

4404019