A high-performance error concealment processor for video decoder

Author

Hsia, Shih-Chang ; Chou, Shih Wen

Author_Institution

Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Taiwan

fYear

2005

fDate

20-24 July 2005

Firstpage

199

Lastpage

202

Abstract

Recently, the video decoding players, such as DVD, VCD, have widely used. However, the image has large distortions as the decoding bit stream from damaged disks. In this study, we develop an error concealment processor for real-time video decoding systems. First, an efficiency algorithm is advised for error concealment with adaptations of the spatial interpolation and the temporal prediction. Based on the adaptive algorithm, real-time VLSI architecture is developed using cell-based design. The complex processing schedule for the error concealment processor is planned as integrated to video decoding systems. The chip occupies one line-buffer and about 27k logic gates using TSMC 0.35μm process. The throughput rate of this error concealment chip can achieve about 50M pixels per second using about 9mm² silicon area.

Keywords

VLSI; adaptive decoding; error correction; logic gates; microprocessor chips; video coding; 0.35 micron; TSMC 0.35μm process; adaptive algorithm; cell-based design; error concealment chip; error concealment processor; logic gates; motion compensation; real-time VLSI architecture; real-time video decoding system; spatial interpolation; temporal prediction; video decoder; Adaptive algorithm; Algorithm design and analysis; DVD; Decoding; Interpolation; Logic gates; Processor scheduling; Real time systems; Streaming media; Very large scale integration; JPEG/MEPG; adaptive; error concealment; interpolation; motion compensation; throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Print_ISBN

0-7695-2403-6

Type

conf

DOI

10.1109/IWSOC.2005.12

Filename

1530941