UMHexagonS algorithm based motion estimation architecture for H.264/AVC

This paper presents an integer pel variable block motion estimation architecture based on JVT accepted UMHexagonS algorithm for H.264/MPEG-4 part 10 (AVC) encoder. The proposed pipelined architecture is capable of calculating the required 41 motion vectors of various size blocks supported by H.264/AVC within a 16×16 block in parallel. The architecture can be used for rapid prototyping of motion estimation core using FPGA. The performance analysis shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of ±16 at a clock speed of around 30 MHz.