Author :
Yin, Haizhou ; Sung, C.Y. ; Ng, H. ; Saenger, K.L. ; Chan, V. ; Crowder, S. ; Zhang, R. ; Li, J. ; Ott, J.A. ; Pfeiffer, G. ; Bendernagel, R. ; Ko, S.B. ; Ren, Z. ; Chen, X. ; Wang, G. ; Liu, J. ; Cheng, K. ; Mesfin, A. ; Kelly, R. ; Ku, V. ; Luo, Z.J. ;
Abstract :
Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in 65nm node and eDRAM in 90nm node have been demonstrated on DSB using the SPE-before-STI scheme
Keywords :
CMOS memory circuits; DRAM chips; SRAM chips; integrated circuit bonding; isolation technology; leakage currents; solid phase epitaxial growth; 65 nm; 90 nm; SRAM; direct silicon bonded substrate; eDRAM; edge defects; high performance bulk CMOS; hybrid crystal orientation technology; leakage current; shallow-trench-isolation; solid phase epitaxy; trench-edge defects; Bonding; CMOS process; CMOS technology; Epitaxial growth; Implants; Leakage current; Semiconductor films; Silicon; Solids; Substrates;
