Wafer level package for image sensor module

A new ISM (image sensor module) WLP (wafer level package) for reflow process is designed, fabricated and tested. The ISM WLP is composed of polymer bonding layer, glass cap wafer for particle free process and CIS (CMOS Image Sensor) chip wafer which has micro via hole interconnection. During the last decades, WLP is highlighted as the next generation ISM Package method for many advantages like high yield (particle free process), small form factor (3D interconnection), low assembly cost and so on. Nevertheless these benefits, there are some problems like micro via hole fabrication, low temperature insulation process (inside hole), bottom side oxide etching, warpage control according to wafer level bonding using different material, and whole process temperature limitation for micro lens damage. Among various fabrication methods for ISM package, COB (Chip on board), COF (Chip on film), and L, T contact WLP from ShellCase are generally used. In case of COB and COF package, it has difficulty in particle control during assembly process. In case of ShellCase type WLP has very complicated fabrication process. Additionally, most of above package has disadvantage in size point of view. Through suggested ISM WLP using through interconnection via, wafer level fabrication & packaging technology is realized. It can not only solve problems of conventional packaging structures but also tremendously reduce the manufacturing & assembly cost (include time) of ISM package and realize real chip scale package. Based on sensor size, 3.67 times 3.42 times 0.39 (H) mm3 WLP is designed. During the parametric study using commercial 3-D simulation programs, silicon thickness, polymer bonding layer thickness, and glass thickness were chose the effective factor. And considering the optical and electrical analysis, we decide the parameter: silicon thickness is 0.1 mm, polymer bonding layer thickness is 0.04 mm, and glass thickness is 0.25 mm. The fabrication process is composed bonding - - layer patterning, wafer bonding, thinning, via etching, passivation layer deposition, bottom oxide opening, metal plating, bottom electrode patterning, solder ball formation, and dicing. A new concept of ISM WLP has been founded to be suitable structure for low cost, small form factor application.