Component-based methodology for hardware design of a dataflow processing network

This paper proposes a new methodology for the design of reusable IP blocks used in data-flow architectures. These IP blocks are elaborated by encapsulating individual operators that constitute part of an algorithm within wrappers that possess a configurable communication layer. This IPs communicates using the VCI protocol, and the interconnections are automatically generated from a data flow graph. The interface wrapper has been designed and simulated in 0.18 μm CMOS technology. When implemented using 2 10-bit input ports, a 12-bit output port and a FIFO depth of 8, synthesis results show that the circuit has a gate count of 1730 NAND gates with a maximum operating frequency of 400 MHz before placement and routing.