DocumentCode
2391119
Title
A high-speed two´s complement bit-sequential multiplier
Author
Lo, Hao-Yung
Author_Institution
Inst. of Inf. Eng., Feng Chia Univ., Taichung, Taiwan
fYear
1994
fDate
22-26 Aug 1994
Firstpage
1040
Abstract
Recently bit-sequential multiplier of hardware designs have become a very active area for VLSI design. The majority of papers deal with unsigned multiplication, very few with signed or two´s complement multiplications. This paper presents a new algorithm for direct two´s complement binary multiplication. It is fast and can easily be fabricated with VLSI technology. In addition to the proposed algorithm of multiplication, numerical examples and structure models are presented to clarify the algorithm
Keywords
VLSI; adders; digital arithmetic; multiplying circuits; VLSI design; binary multiplication; carry-save adders; hardware designs; signed multiplication; two´s complement bit-sequential multiplier; unsigned multiplication; Algorithm design and analysis; Counting circuits; Design methodology; Hardware; Shape; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994
Print_ISBN
0-7803-1862-5
Type
conf
DOI
10.1109/TENCON.1994.369158
Filename
369158
Link To Document