Efficient designs of unified 2´s complement division and square root algorithm and architecture

Efficient unified 2´s complement division and square root algorithm, and their architectures are proposed in this work. The designs are high speed, small area and high compatibility. The architectures provide bit level pipelined operation, as well as parallel remainder iteration and its sign detection operations. A simplified signed digit addition (SDA) scheme without carry propagation delay is adopted. As such, their cycle time is minimized down to a carry save addition time. Moreover, a fast deposition scheme of 2´s complement (TC) into the sign magnitude (SM) architecture is developed, which incurs no time penalty. A fast online algorithm for number conversion from SM results to TC output is also devised. The algorithm performs faster than the known online conversion algorithms. Most importantly, the unified divider/square rooter have more regular geometry than the known designs, and accordingly suitable for VLSI implementation