A low-power partitioning methodology by maximizing sleep time and minimizing cut nets

The rising objective in VLSI design is to minimize the average power consumption. Sleep time maximization along with minimization of cut nets are explored as ways to decrease and minimize the power consumption. The major motivation is to deactivate parts of a circuit when they are idle, while simultaneously keeping the cut nets as low as possible. This dual objective problem is separately formulated as two single objectives and then combined into one normalized objective function. The joint problem is shown to be NP-hard, hence heuristic approaches were introduced. A modified version of the genetic algorithm is presented along side with an efficient implementation of a geometric iterative improvement technique using segmented trees. Results are presented for three hypothetical test cases and the results demonstrate more than 40% improvement.