• DocumentCode
    2391566
  • Title

    Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models

  • Author

    Ishibashi, Koichiro ; Ohbayashi, Shigeki ; Eikyu, Katsumi ; Tanizawa, Motoaki ; Tsukamoto, Yasumasa ; Osada, Kenichi ; Miyazaki, Masayuki ; Yamaoka, Masanao

  • Author_Institution
    Renesas Technol. Corp., Tokyo
  • fYear
    2006
  • fDate
    11-13 Dec. 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability
  • Keywords
    MOSFET; SPICE; low-power electronics; semiconductor device models; system-on-chip; MOS transistors; Spice models; circuit technology; electrical stability; low power SOC; power reduction; transistor models; CMOS logic circuits; CMOS technology; Delay effects; Frequency; Large scale integration; MOSFETs; Moore´s Law; Stability analysis; Timing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2006. IEDM '06. International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    1-4244-0438-X
  • Electronic_ISBN
    1-4244-0439-8
  • Type

    conf

  • DOI
    10.1109/IEDM.2006.346996
  • Filename
    4154431
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2391566