Title :
An FPGA based accelerator for SAT based combinational equivalence checking
Author :
Safar, Mona ; El-Kharashi, M. Watheq ; Salem, Ashraf
Author_Institution :
Dept. of Comput. & Syst. Eng., Ain Shams Univ., Cairo, Egypt
Abstract :
In this paper we present software/reconfigurable hardware SAT accelerator for combinational equivalence checking. The SAT binary clauses are mapped into an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict detector implemented on FPGA. The validity of the proposed approach is shown through the ISCAS´85 benchmark circuits.
Keywords :
combinatorial mathematics; computability; field programmable gate arrays; reconfigurable architectures; binary clauses; clause evaluator; combinational equivalence checking; conflict detector; field programmable gate arrays; implication graph; indexed clause database; software/reconfigurable hardware SAT accelerator; ternary clauses; Binary decision diagrams; Business continuity; Computer graphics; Concurrent computing; Databases; Detectors; Engines; Field programmable gate arrays; Hardware; Reconfigurable logic;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN :
0-7695-2403-6
DOI :
10.1109/IWSOC.2005.40
