Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS

Author

Hayashi, T. ; Nishida, Y. ; Sakashita, S. ; Mizutani, M. ; Yamanari, S. ; Higashi, M. ; Kawahara, T. ; Inoue, M. ; Yugami, J. ; Tsuchimoto, J. ; Shiga, K. ; Murata, N. ; Sayama, H. ; Yamashita, T. ; Oda, H. ; Kuroi, T. ; Eimori, T. ; Inoue, Y.

Author_Institution

Production & Technol. Unit, Renesas Technol. Corp., Hyogo

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS

Keywords

CMOS integrated circuits; MISFET; hafnium compounds; high-k dielectric thin films; ion implantation; optimisation; reliability; silicon compounds; titanium compounds; LSTP CMISFETs; Si-TiN-HfSiON; dual metal CMOS; fluorine ion implantation; gate depletion; high-k dielectric; high-reliability; hybrid gate dielectric; nMIS; optimization; pMIS; poly-silicon gate; CMOS process; Costs; Dielectric substrates; Fabrication; Hafnium; High K dielectric materials; High-K gate dielectrics; Production; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0438-X

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.347009

Filename

4154444