Title :
Method for acceleration of logic simulations
Author :
Sakakura, Masayoshi ; Fukazawa, Yoshiaki
Author_Institution :
Centre for Inf., Waseda Univ., Tokyo, Japan
Abstract :
We present a method for acceleration of logic simulations. The logic simulation is mainly used to detect malfunctions in the logical design phase. As the size of logical circuits grows, acceleration of the logic simulation becomes increasingly required. Several acceleration methods have been presented for this purpose. The outstanding feature of our method is that it accelerates the simulation speed in accordance with the dynamic behaviours of target circuits. A global dynamic behaviour is predicted to realize this feature, through the investigation of the relationship among gates in the early stage of the simulation. Using the relationships, a logic simulation is accelerated by a process called “grouping”. We have confirmed that the dynamic information of the circuits accelerates logical simulation by the evaluation system
Keywords :
circuit analysis computing; digital simulation; logic CAD; acceleration; acceleration methods; dynamic behaviour; evaluation system; gates; global dynamic behaviour; grouping; logic simulation; logic simulations; logical circuits; logical design phase; malfunctions; simulation speed; Acceleration; Circuit simulation; Computational modeling; Computer science; Discrete event simulation; Informatics; Logic circuits; Logic design; Marine vehicles; Predictive models;
Conference_Titel :
TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994
Print_ISBN :
0-7803-1862-5
DOI :
10.1109/TENCON.1994.369195