A layout driven test generation for CMOS combinational circuits

Author

Bhattacharya, U.K. ; Gupta, I. Sen

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

1994

fDate

22-26 Aug 1994

Firstpage

823

Abstract

This paper presents a test generation scheme for CMOS combinational circuits. The fault model has been chosen from the layout description of the circuit as the set of faults that are more likely to occur. A divide-and-conquer strategy has been used for test generation, whereby explicit fault simulation is avoided over the entire circuit. The developed fault model and the test generation algorithms have been applied to some example circuits

Keywords

CMOS digital integrated circuits; circuit analysis computing; combinational circuits; digital simulation; divide and conquer methods; integrated circuit testing; logic testing; CMOS combinational circuits; divide-and-conquer strategy; fault model; fault simulation; layout description; layout driven test generation; test generation; test generation algorithms; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; MOS devices; MOSFETs; Monitoring; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994

Print_ISBN

0-7803-1862-5

Type

conf

DOI

10.1109/TENCON.1994.369196

Filename

369196

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2391849