Title :
Very high-speed Reed-Solomon decoders
Author :
Sarwate, Dilip V. ; Shanbhag, Naresh R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A pipelined finite-field multiplier structure in conjunction with a single systolic array implementation of the Berlekamp-Massey algorithm leads to a highly parallel decoder architecture in which the critical path delay is an order of magnitude smaller than the path delays of conventional architectures
Keywords :
Reed-Solomon codes; VLSI; delays; iterative decoding; multiplying circuits; pipeline processing; systolic arrays; Berlekamp-Massey algorithm; VLSI; critical path delay; iterative method; parallel decoder architecture; pipelined finite-field multiplier structure; systolic array implementation; very high-speed Reed-Solomon decoders; CMOS technology; Computer architecture; Concurrent computing; Delay; Iterative algorithms; Iterative decoding; Iterative methods; Polynomials; Reed-Solomon codes; Systolic arrays;
Conference_Titel :
Information Theory, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Sorrento
Print_ISBN :
0-7803-5857-0
DOI :
10.1109/ISIT.2000.866717
