Experimental results for single test point insertion using testability analysis

In this paper a new scheme to find methods for test point insertion, into combinational logic circuits, using testability values from testability analysis is proposed. Exhaustive simulation is done by placing an insertion line into every node in the circuit one at a time. Fault coverage is noted before and after the insertion. A few testability analysis techniques e.g. SCOAP and our modified distance techniques are used. The experiment is carried out to see which testability analysis technique could select an insertion line that would give the optimum fault coverage compared to the results from the simulation. The ISCAS85 benchmark circuits are used as the basis for the comparison. The insertion could be useful when there are few spare pins on an IC package and if we wanted to use them as insertion lines to improve testability of the circuit. The results showed that the distance techniques gave the best improvement in fault coverage