DocumentCode
2391960
Title
Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications
Author
Li, Miao ; Noel, Peter ; Kwasniewski, Tad ; Wang, Shoujun
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2005
fDate
20-24 July 2005
Firstpage
500
Lastpage
502
Abstract
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-μm CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34" FR4 backplane.
Keywords
CMOS integrated circuits; clocks; data communication; decision feedback equalisers; intersymbol interference; radio receivers; 0.18 micron; 6.25 Gbit/s; 8 Gbit/s; CMOS technology; DFE circuit design; FR4 backplane; decision feedback equalization; high-speed backplane data communication; inter-symbol interference; quarter-rate clock timing; Backplanes; CMOS technology; Clocks; Data communication; Decision feedback equalizers; Delay; Finite impulse response filter; High speed integrated circuits; Intersymbol interference; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN
0-7695-2403-6
Type
conf
DOI
10.1109/IWSOC.2005.48
Filename
1530998
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