• DocumentCode
    2392104
  • Title

    Configurable workload generators for multicore architectures

  • Author

    Panda, Amayika ; Avakian, Annie ; Vemuri, Ranga

  • Author_Institution
    Sch. of Electron. & Comput. Syst., Univ. of Cincinnati, Cincinnati, OH, USA
  • fYear
    2011
  • fDate
    26-28 Sept. 2011
  • Firstpage
    179
  • Lastpage
    184
  • Abstract
    Proposed multicore architectures are usually evaluated using two types of benchmarks: application and synthetic. Application benchmarks use well understood computations to generate well defined workloads. In contrast, synthetic benchmarks are tunable to generate a range of custom workloads. Both classes are currently limited. Existing application benchmarks are inflexible. And the options offered by synthetic benchmarks are too limited to generate a large variety of workload patterns. In this paper we propose novel workload generation methodologies that allow system developers to generate custom benchmarks for desired workload conditions for a variety of existing and multicore architectures. Specifically we describe two configurable workload generators, which we name ConWork and CompWork. ConWork is a configurable synthetic workload generator using which artificial traffic among the processors and memories can be generated. CompWork is a configurable computational workload generator, which can be used to specify vector and matrix applications so as to elicit the desired computational workloads among the processors. Together the two generators provide a number of options to generate workloads to evaluate a variety of performance metrics of existing and emerging multicore architectures including bus based SoCs, packet switching NoCs and hybrids.
  • Keywords
    multiprocessing systems; network-on-chip; parallel architectures; system-on-chip; CompWork; ConWork; application benchmarks; bus based SoC; configurable workload generators; matrix applications; multicore architectures; packet switching NoC; vector applications; Benchmark testing; Generators; Instruction sets; Multicore processing; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2011 IEEE International
  • Conference_Location
    Taipei
  • ISSN
    2164-1676
  • Print_ISBN
    978-1-4577-1616-4
  • Electronic_ISBN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2011.6085077
  • Filename
    6085077