DocumentCode
2392192
Title
Transaction analysis of multiprocessor based platform with bus matrix
Author
Lee, Seungbeom ; Park, Sin-Chong
Author_Institution
Inf. & Commun. Univ., Daejeon, South Korea
fYear
2005
fDate
20-24 July 2005
Firstpage
552
Lastpage
556
Abstract
This paper presents an analysis of transaction of multiprocessor platform with bus matrix. Simple equations about the latency and throughput for this architecture are derived. From this equation we evaluate operating frequency to meet latency and throughput requirements. This architecture is modeled as transaction level model (TLM) in SystemC in order to confirm the validation of the governing equation. The result of simulation corresponds to that of the derived equation.
Keywords
integrated circuit modelling; microprocessor chips; multiprocessing systems; system buses; system-on-chip; SystemC; bus matrix; multiprocessor based platform; transaction analysis; transaction level model; Costs; Delay; Equations; Frequency; Information analysis; Semiconductor device manufacture; Testing; Throughput; Time to market; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN
0-7695-2403-6
Type
conf
DOI
10.1109/IWSOC.2005.108
Filename
1531009
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