A novel methodology for Multi-Project System-on-a-Chip

In this paper, a novel silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. For integrating heterogeneous SoC projects into a single chip, the current SoC methodology is insufficient due to the complexity of MP-SoC. In order to improve the robustness of MP-SoC design and verification, a new design flow was developed. It consists of a virtual platform, a logical implementation, a rapid prototyping platform, a physical implementation, and testing stages. The virtual platform is a system modeling and hardware/software co-design system by using electronic system level (ESL). VIP system is adopted for the AMBA-compliant check of the interfaces of the MP-SoC. In addition, STEAC and DFT were used to facilitate MP-SoC testing integration. The rapid prototyping platform called “CONCORD” which has characteristics of connection flexibility, modularization, and consistence architecture for emulating the hardware of MP-SoC before chip being taped out. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about 37.97mm² in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm² by implementing these projects separately, the results show that there are 91.42 mm² or 70.6 % silicon area reduced by this novel silicon prototyping methodology.