A highly-parallel architecture for concurrent rule match of AI production systems

In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. The architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. The set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. The analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher