The design and analysis of fault-tolerant VLSI/WSI array processors

Most of the previous literature predict the yield of fault tolerant VLSI/WSI arrays first adopting the fault-free switching network, by only considering the step of reconfiguration algorithm, and assuming the steps of placement, routing and switch programming are all perfect. Consequently, this simplified yield estimation model may give quite misleading results. The paper proposes an effective reconfiguration process which comprises the reconfiguration, placement, routing and switch programming algorithms and develops a thorough yield simulation tool for the proposed reconfiguration process and redundancy schemes. To be accurate, in our yield simulation, we take both the PE and switch failures into account. Therefore, our yield prediction model will provide more precise and meaningful data. This yield simulation tool can also offer the information of performance degradation probability distribution, reconfiguration, placement, routing and switch programming algorithm survival probability. The yield simulation is performed to validate our redundancy schemes