Title :
FPGA implementation of a deterministic bit-stream neuron
Author :
Bostan, I. ; Ionescu, V. ; Moldovan, C.
Author_Institution :
Electron. Dept., Univ. of Pitesti, Romania
fDate :
28 Sept.-2 Oct. 2003
Abstract :
This paper presents a digital hardware implementation of a deterministic Bit-Stream Artificial Neuron (AN) with ten inputs. The design was made to be implemented in a FPGA device for a minimal hardware requirement. The simulation for XCV3200 Virtex FPGA device, showed the possibility to place around 200 neurons (including the extra logic required to run the networks). As each neuron has ten connections this means that it will be possible to place a network with 2000 weights.
Keywords :
field programmable gate arrays; neural nets; FPGA implementation; XCV3200 Virtex FPGA device; deterministic bit-stream neuron; digital hardware implementation; minimal hardware requirement; Application software; Artificial neural networks; Field programmable gate arrays; Logic design; Logic devices; Neural network hardware; Neurons; Object oriented modeling; Programmable logic arrays; Stochastic processes;
Conference_Titel :
Semiconductor Conference, 2003. CAS 2003. International
Print_ISBN :
0-7803-7821-0
DOI :
10.1109/SMICND.2003.1252456
