FPGA implementation of a Boolean neuronal network

This paper presents the model of Boolean neuronal network. This model of neuron considers inputs and outputs to be binary and the weight controls function to be the multiplexer of some bases binary relations. The neuron body is a threshold gate which can implement different functions. The neuron was designed using a "multiplexer" of Boolean functions, a random hardware circuit for weight and a majority circuit for the body. The network was designed using top-level structural description with neuron as an object and it was implemented in a FPGA structure.