Title :
VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes
Author :
Shieh, Ming-Der ; Fang, Shih-Hao ; Tang, Shing-Chung ; Yang, Der-Wei
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.
Keywords :
VLSI; cyclic codes; decoding; integrated circuit design; memory architecture; parity check codes; LDPC decoder; VLSI design; area-efficient memory access architectures; quasicyclic LDPC codes; small memory blocks; Decoding; Delay; Memory architecture; Memory management; Merging; Parallel architectures; Parity check codes;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085108
