Title :
A multi-segment clocking scheme to reduce on-chip EMI
Author :
Mesgarzadeh, Behzad ; Zadeh, Iman Esmaeil ; Alvandpour, Atila
Author_Institution :
Linkoping Univ., Linköping, Sweden
Abstract :
This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.
Keywords :
CMOS integrated circuits; VLSI; clocks; electromagnetic interference; harmonics suppression; interference suppression; CMOS process; VLSI circuits; electromagnetic radiations; harmonic tones suppression; multisegment clock signal; multisegment clocking scheme; on-chip EMI reduction technique; relaxed edge rate; short-circuit power dissipation; size 65 nm; Clocks; Electromagnetic interference; Electromagnetic radiation; Harmonic analysis; Power dissipation; Power system harmonics; System-on-a-chip;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085110