Title :
Low power tri-state register files design for modern out-of-order processors
Author :
Gong, Na ; Tang, Geng ; Wang, Jinhui ; Sridhar, Ramalingam
Author_Institution :
Univ. at Buffalo, State Univ. of New York, Buffalo, NY, USA
Abstract :
In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7-14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4-17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.
Keywords :
microprocessor chips; power aware computing; power consumption; architectural level technique; checkpoint-based microprocessor; high-performance microprocessor; integrated circuit technique; out-of-order processor; power consumption; power reduction; reorder buffer-based microprocessor; size 32 nm; tri-state register files design;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085113
