• DocumentCode
    2392944
  • Title

    High performance multi-engine regular expression processing

  • Author

    Arumugam, Thianantha ; Sezer, Sakir ; Burns, Dwayne ; Vasu, Vishalini

  • Author_Institution
    Inst. of Electron., Commun., & Inf. Technol. (ECIT), Queen´´s Univ., Belfast, UK
  • fYear
    2011
  • fDate
    26-28 Sept. 2011
  • Firstpage
    347
  • Lastpage
    352
  • Abstract
    This paper discusses a novel multi-engine hardware based regular expression processor. Regular expression is widely used as a pattern matching technique to detect presence of malicious content in Internet traffic. In the proposed approach, parallel IP flows are handled by separate regular expression processing engines, sharing a common program memory. The proposed architecture has been designed and implemented for a four engine system using Altera Stratix IV technology. With four independent engines operating at 185.43 MHz the achievable system bandwidth is estimated to be 5.93 Gbps, using approximately 20K ALUTs.
  • Keywords
    Internet; computer network security; field programmable gate arrays; Altera Stratix IV technology; FPGA technology; Internet protocol; Internet traffic; communication network security; field programmable gate array; frequency 185.43 MHz; malicious content detection; multiengine hardware; multiengine regular expression processing; parallel IP flow; pattern matching technique; Computer architecture; Engines; Field programmable gate arrays; Hardware; IP networks; Pattern matching; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2011 IEEE International
  • Conference_Location
    Taipei
  • ISSN
    2164-1676
  • Print_ISBN
    978-1-4577-1616-4
  • Electronic_ISBN
    2164-1676
  • Type

    conf

  • DOI
    10.1109/SOCC.2011.6085117
  • Filename
    6085117