Design of a neural recording amplifier with tunable pseudo resistors

This paper describes a voltage-controlled pseudo-resistor with widely available operating voltage range applied to neural recording amplifier designs. The proposed pseudo-resistor which consists of serial-connected PMOS device and an auto-tuning circuit provides ultra-high resistance to cancel DC offset from electrode-electrolyte interface. The proposed design has been estimated in standard CMOS 0.18-μm process, achieving midband gain of 40 dB, bandwidth from 0.4 Hz to 7 kHz, input-referred noise of 5.98 μVrms, calculated NEF of 7.2, and 3.1-μW power consumption.