Title :
Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
Author :
Deivasigamani, Meganathan ; Tabatabaei, Shaghayeghsadat ; Mustafa, Naveed ; Ijaz, Hamza ; Aslam, Haris Bin ; Liu, Shaoteng ; Jantsch, Axel
Author_Institution :
Dept. of Electron. Eng., Anna Univ., Chennai, India
Abstract :
This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 8×8 mesh architecture and its performance is evaluated.
Keywords :
network-on-chip; parallel algorithms; NoC fabric; exhaustive parallel search algorithm; forward wave propagation manner; mesh architecture; network-on-chip; setup path; Clocks; Q measurement; Search methods; Switches; Circuit-switch (CS); Exhaustive Parallel Search (EPS); Guaranteed Throughput (GT); Network-on-Chip (NoC);
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085123
