Title :
Design of complex circuits using the Via-Configurable transistor array regular layout fabric
Author :
Pons, Marc ; Moll, Francesc ; Rubio, Antonio ; Abella, Jaume ; Vera, Xavier ; Gonzalez, Adriana
Author_Institution :
Electron. Eng., Univ. Politec. de Catalunya, Barcelona, Spain
Abstract :
Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.
Keywords :
CMOS integrated circuits; integrated circuit design; transistor circuits; CAD tool; CMOS technology; complex circuit; regular layout generation; regularity constraint; size 45 nm; via-configurable transistor array regular layout fabric; Arrays; Fabrics; Layout; Metals; Routing; Simulated annealing; Transistors;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085126
