Title :
Scheduling of transactions for system-level test-case generation
Author :
Emek, Roy ; Naveh, Yehuda
Author_Institution :
IBM Haifa Res. Lab., Israel
Abstract :
We present a methodology for scheduling system-level transactions generated by a test-case generator. A system, in this context, may be composed of multiple processors, busses, bus-bridges, memories, etc. The methodology is based on an exploration of scheduling abilities in a hardware system. In its focus is a language for specifying transactions and their ordering. Through the use of hierarchy, the language provides the possibility of applying high-level scheduling requests. The methodology is realized in X-Gen, a system-level test-case generator used in IBM. The model and algorithm used by this tool are also discussed.
Keywords :
automatic test pattern generation; formal verification; hardware description languages; high level synthesis; processor scheduling; X-Gen generator; bus-bridges; compact graphical language; functional verification; hardware system scheduling abilities; high-level scheduling requests; multiple processors; multiple-transaction scheduling; state-machine operations; system-level test-case generation; transactions scheduling; Computer bugs; Engines; Hardware; Laboratories; Logic testing; Processor scheduling; System testing; System-on-a-chip; Timing; Vehicles;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-8236-6
DOI :
10.1109/HLDVT.2003.1252489
