Title :
Well tapping methodologies in power-gating design
Author :
Shi, Kaijian ; Tester, David
Author_Institution :
Cadence Design Syst., Dallas, TX, USA
Abstract :
65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.
Keywords :
CMOS integrated circuits; integrated circuit layout; CMOS designs; cell density; cell efficiency; chip area; design schedule; layout complexity; leakage power; power-gating designs; size 65 nm; tapless library cells; well tapping methodologies; Logic gates; Power supplies; Rails; Silicon; Switches; Timing;
Conference_Titel :
SOC Conference (SOCC), 2011 IEEE International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1616-4
Electronic_ISBN :
2164-1676
DOI :
10.1109/SOCC.2011.6085133
