Toward High Accuracy Transaction Level Energy Modeling for System-on-Chip Buses

Our daily life now heavily depends on various electronic appliances, which are typically operated by one or more IC chips. Such chips are designated as System-on-Chips (SoCs) when they integrate a CPU and a set of peripheral modules. Due to the worldwide strong momentum to pursue green technology, low energy has become a key requirement for modern SoCs. In this work, we developed an energy modeling framework to capture the energy consumption characteristics of SoC buses in early design stages. In this framework, the SoC design is abstracted at the transaction level for high simulation throughput, but the parameters of the energy model are extracted from register-level simulations of micro-benchmarks to guarantee good correlation with real circuit behaviors. The energy model has been integrated into a SoC simulator for industry-strength SoC designs.