Logic simulation using T-algorithm on network of workstations

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulation algorithms is by exploiting the inherent parallelism in the sequential version. We propose a T-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network. The main objective has been to balance the computational load among the processors and at the same time reduce the communication to a bare minimum. We have achieved these by partitioning the circuit into cones containing gates in a fanout free region (FFR). Further, the cones of FFRs at the same level (having the same distance from primary inputs) are assigned by the master processor and communicated to the other workstations through the network. We have kept the balance on the computational load among slave processors by assigning a proper number of FFR cones, using a good heuristic. We have also shown that FFR partitioning reduces the amount of communication between the processors