Title :
Static Dual Edge Flip Flop Implementations on the 90nm Process
Author :
Constantino, J.B.A. ; Madamba, Joy Alinda R.
Author_Institution :
Electr. & Electron. Eng. Inst., Univ. of the Philippines, Malabon City, Philippines
Abstract :
Dual edge triggered flip flops has twice the throughput, so they can be run at half the frequency to reduce power consumption at the clock distribution network. Three Dual edge flips were compared with each other. C-DDR-FF has the lowest power consumption due to its very simple structure, Ep-dsff has the lowest area due to the sharing of the clock pulse generator, while CBS-FF has the fastest speed due to its fast hold time constraints. However, they present no advantage against single edge flip flops.
Keywords :
clock distribution networks; flip-flops; nanotechnology; power consumption; pulse generators; 90nm process; C-DDR-FF; clock distribution network; clock pulse generator; dual edge triggered flip flops; power consumption reduction; static dual edge flip flop implementations; Clocks; Delay; Inverters; Latches; Power demand; Pulse generation; Transistors;
Conference_Titel :
Modelling Symposium (AMS), 2011 Fifth Asia
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4577-0193-1
DOI :
10.1109/AMS.2011.55
