Title :
Gate dielectric scaling for high-performance CMOS: from SiO2 to high-K
Author :
Chau, Robert ; Datta, Suman ; Doczy, Mark ; Kavalieros, Jack ; Metz, Matthew
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.
Keywords :
CMOS integrated circuits; MOSFET; dielectric materials; dielectric thin films; silicon; silicon compounds; 45 nm; CMOS; NMOS transistors; PMOS transistors; SiO/sub 2/-Si; bulk Si; dielectric-metal-gate stacks; gate dielectric scaling; logic technology node; CMOS logic circuits; CMOS technology; Dielectric measurements; Electric variables measurement; Gate leakage; High K dielectric materials; High-K gate dielectrics; Logic devices; MOS devices; MOSFETs;
Conference_Titel :
Gate Insulator, 2003. IWGI 2003. Extended Abstracts of International Workshop on
Conference_Location :
Toyko, Japan
Print_ISBN :
4-89114-037-2
DOI :
10.1109/IWGI.2003.159198
