Title :
Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology
Author :
Hwang, Y.N. ; Hong, J.S. ; Lee, S.H. ; Ahn, S.J. ; Jeong, G.T. ; Koh, G.H. ; Kim, H.J. ; Jeong, W.C. ; Lee, S.Y. ; Park, J.H. ; Ryoo, K.C. ; Horii, H. ; Ha, Y.H. ; Yi, J.H. ; Cho, W.Y. ; Kim, Y.T. ; Lee, K.H. ; Joo, S.H. ; Park, S.O. ; Jeong, U.I. ; Jeong
Author_Institution :
Adv. Technol. Dev., Samsung Electron. Co. Ltd, Kyunggi-Do, South Korea
Abstract :
We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 μm-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge2Sb2Te5, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.
Keywords :
CMOS integrated circuits; MOSFET; antimony compounds; chalcogenide glasses; germanium compounds; random-access storage; 0.2 V; 0.24 micron; 0.6 mA; 2 mA; BL clamping circuits; CMOS technology; Co salicidation; GeSbTe; MOS transistors; cell perturbation; cell structure; draw back current; driving current; enlarge fabrication tolerance; integrated phase-change chalcogenide random access memory; phase-change chalcogenide nonvolatile RAM; reliable phase-transitions; sensing signal; transistor formation; twin cell; CMOS technology; Clamps; Fabrication; Integrated circuit technology; Low voltage; MOSFETs; Nonvolatile memory; Random access memory; Read-write memory; Tellurium;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252543
